The Chapter 74 of IEEE802.3ap-2007, the latest version of which is IEEE 802.3-2008, and IEEEP802.3D1.2 define an FEC (Forward Error Correction) sublayer applied to a BASE-R physical layer of 10G Ethernet. The criterion of the FEC sublayer reduces the BER rate of a system from 10−7 to 10−12. Also, this criterion is applicable to applications of 40G/100G Ethernet.
In order to be compatible with different Ethernet application layers, protocols provide that the FEC layer compresses an original frame header to leave space so as to load an FEC check bit, thus assuring that the layer keeps the same frame length (the frame length defined in the Chapter 74 of IEEE 802.3ap-2007 is 2112 bits) as other application layers. However, such a processing method results in a reception terminal being very difficult to identify frame boundaries between respective frames and requiring a great deal of time to synchronize with frames of a transmission terminal so as to find out correct positions of the frame boundaries.
FIG. 1 shows a structural diagram of an FEC decoding system, which receives the input from a PMA (PHYSICAL MEDIUM ATTACHMENT) layer and outputs a processing result to a PCS (PHYSICAL CODING SUBLAYER) layer, defined in the Chapter 74 of IEEE 802.3ap-2007. The FEC decoding system includes five modules: a shifter, which shifts data received from the PMA layer; a PN-2112 generator, which is used to generate a PN2112 sequence which will be used to apply an XOR logic operation with the data shifted by the shifter to carry out a descrambling operation on the received data; the data shifted by the shifter are input into a FEC decoder after the XOR operation is applied to the data generated by the PN-2112 generator; and the FEC decoder, which performs Forward Error Correction on the input data, and outputs the error-corrected data. The output data pass through a 65/66 data block restoration module, which is capable of performing a frame header restoration on the FEC-decoded data and restoring the payload of 2080 bits in each FEC frame data into 32 frames of PCS frame with a length of 66 bits, and then the output of the module enters into the PCS layer. The FEC decoder further outputs the generated syndrome to a synchronization controller for the control of the FEC synchronization, and the output of the synchronization controller is sent to the shifter so as to control the shift operation.
The FEC decoder itself further comprises a syndrome generator, trapper and pattern corrector. The FEC decoder is used for Forward Error Correction, but it also is used for the frame synchronization with the transmission terminal due to the particularity of relevant protocols of the present invention.
A synchronization procedure used by the circuit structure of FIG. 1 includes the following steps:
a) an assumed position of the frame boundary is tested;                a1) a position of frame boundary is assumed by the shifter, and taking the assumed position of frame boundary as a start, the PN-2112 generator is used to perform a descrambling operation on the received data; and        a2) the syndrome generator performs a FEC check on the data of one frame which takes the assumed frame boundary as a start position;                    i) if the check is not matched (the received check bit is not equal to the check bit obtained from the operation), the synchronization controller may control the shifter to make the assumed position of frame boundary leap over a position of one bit, and then step a) is retried;                        
b) for one assumed frame boundary, the synchronization controller may confirm all FEC checks for consecutive n frames to be correct according to the output results of the syndrome generator;                b1) if the FEC check for any one of the consecutive n frames is incorrect, the synchronization controller may control the shifter to make the assumed position of frame boundary leap over a position of one bit, and the entire frame synchronization procedure is restarted; and        b2) if the synchronization controller detects that all FEC checks for the received consecutive n frames are correct, it is to enter into step c);        
c) the frame synchronization is established; and
d) if the synchronization controller detects that all FEC checks for the received consecutive m frames are incorrect, the frame synchronization is considered to be lost, and the entire frame synchronization procedure is restarted.
For a frame length of 2112 bits, the above steps are repeated for 2112 times at most to traverse all of 2112 possible positions to find out the correct position of frame boundary. In the above description, representative data is taken as m=8, n=4.
FIG. 2 schematically shows how a general method performs the frame synchronization. According to FIG. 2, at the beginning, the frame synchronization logic cannot determine the correct start position, thus needs to assume a frame start position in a frame to check this frame. However, when the data of the last bit of a first frame enters into the frame synchronization logic, the frame synchronization logic cannot generate the check result for this frame immediately. This is because there may be a delay caused by a pipeline structure based design in the hardware implementation. The delay, caused by some functional logic such as descrambling logic, is unavoidable. After the pipeline delay has been incurred, if the frame synchronization logic detects that the position of the first frame boundary is incorrect, the frame synchronization logic needs to make the subsequently assumed position of frame boundary leap over one bit as the next assumed frame boundary. At this time, due to the pipeline delay as shown in FIG. 2, it is too late to begin detecting the data of the second frame after one bit is leaped over from the start position of the frame boundary of a second frame. Consequently, the frame synchronization logic has to discard the second frame and begin sampling a third frame. The frame synchronization logic may leap over one bit based on the frame boundary of the third frame, and repeat the check operation in the first frame on the third frame.
In this way, in the worst case, the frame synchronization logic needs to detect 2112 frames, to discard 2111 frames, and to carry out the operation of leaping over one bit for 2111 times. This needs to take (2112+2111)*2112+2111=8,921,087 BT (bit time) to obtain a correct frame boundary, that is, a correct start bit of a frame. Compared with other high speed interfaces with similar rate (about 600,000BT for SATA2.0 and 500,000BT for PCIE2.0), such frame synchronization time is much longer.